- Jobs
ResumeCreate your job-winning resume using our free resume builder.
PortfolioShowcase your skills and projects with a professional portfolio.ResumeCreate your job-winning resume using our free resume builder.Resume BuilderMake a resume for free.Resume TemplatesAccess our extensive library of professional & ready-to-use templates.Resume ExamplesGet inspired by real resume examples to create your own.Occupation GuideAccess resume writing guides tailored for different professions.Resume HelpGet expert advice on all things resume from our team of recruitment specialists.- ResourcesSuccess StoriesBusiness ExcellenceAbout CakeResumeFeatured Reads
- Hire
- Download our App
Jobs
The employer was active about 6 hours ago
1. ASIC Design or IP Integration 2. Familiar with Digital front-end EDA tool.
1. ASIC Design or IP Integration 2. Familiar with Digital front-end EDA tool.
300台灣新竹市, 新北市, 台灣
1.8M ~ 2.5M TWD / year
3 years of experience required
No management responsibility
• 面板驅動IC 或 SoC 設計
• 面板驅動IC 或 SoC 設計
300台灣新竹市東區
2.5M ~ 3.5M TWD / year
5 years of experience required
No management responsibility
面板驅動IC或SOC設計 影像處理與影像壓縮設計 高速介面數位控制(如MIPI/ISP等)
面板驅動IC或SOC設計 影像處理與影像壓縮設計 高速介面數位控制(如MIPI/ISP等)
台灣新竹市新竹
1.8M ~ 3M TWD / year
1 years of experience required
No management responsibility
工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計
工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計
Hsinchu, Hsinchu City, Taiwan
4M ~ 5M TWD / year
6 years of experience required
Managing 1-5 staff
1.Micro-architecture / RTL design, simulation and verification 2.Chip integration, algorithm implementation or interface design. 3.Familiar CDC, synthesis, formality and STA flow 4. Familiar with F...
1.Micro-architecture / RTL design, simulation and verification 2.Chip integration, algorithm implementation or interface design. 3.Familiar CDC, synthesis, formality and STA flow 4. Familiar with F...
Taipei, Taiwan
1.5M ~ 2.5M TWD / year
3 years of experience required
No management responsibility
1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2....
1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2....
114台灣台北市內湖區, 302台灣新竹縣竹北市
3M ~ 4M TWD / year
10 years of experience required
No management responsibility